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fedl610473-07 issue date jan. 7, 2013 ml610471/472/473/q471/q472/q473 8-bit microcontroller with a built-in lcd driver general description this lsi is a high performance cmos 8-bit microcontroller equipped with an 8-bit cpu nx-u8/100 and integrated with peripheral functions such as the uart, rc oscillation type a/d converter, and lcd driver. the cpu nx-u8/100 is capable of efficient instruction execution in 1-intruction 1-clock mode by 3-stage pipe line architecture parallel processing. additionally, it adopts the low-/high-speed dual clock system, standby mode, and process that prohibits leak current at high temperatures, and is most suitable for battery-driven applications. mtp version (ML610Q471/ml610q472/ml610q473) can rewrite programs on-board, which can contribute to reduction in product development tat. the flash memory incorporated into this mtp version implements the mask rom-equivalent low-voltage operation (1.25v or higher) and low-power consumption (typically 5ua at low-speed operation), enabling volume production by the mtp version. for industrial use, ml610471p/ml610472p/ml610473p/ML610Q471p/ml610q472p/ml610q473p with the extended operating ambient temperature ranging from -40c to 85c are available. features ? cpu - 8-bit risc cpu (cpu name: nx-u8/100) - instruction system: 16-bit length instruction - instruction set: transfer, arithmetic operations, comparison, logic operations, multiplication/division, bit manipulations, bit logic operations, jump, conditional jump, call return stack manipulations, arithmetic shift, and so on - flash memory rewrite function (mtp version only) - minimum instruction execution time 30.5 s (@ 32.768 khz system clock) 2 s (@ 500 khz system clock) ? internal memory - ml610471/ml610472/ml610473 internal 8kbyte mask rom (4k x 16 bits) (including unusable 256byte test area) internal 512byte ram (512 x 8 bits) - ML610Q471/ml610q472/ml610q473 internal 8kbyte flash rom (4k x 16 bits) (including unusable 256byte test area) internal 512byte ram (512 x 8 bits) ? interrupt controller - 1 non-maskable interrupt source: internal source: 1 (watchdog timer) - 12 maskable interrupt sources: internal source: 8 (timer 2, timer 3, uart0, rc oscilla tion type a/d converter, tbc128hz, tbc32hz, tbc16hz, tbc2hz) external source: 4 (p00, p01, p02, p03) ? time base counter - low-speed time base counter x 1 channel frequency compensation (compensation range: approx. -488ppm to +488ppm. compensation accuracy: approx. 0.48ppm) - high-speed time base counter x 1 channel ? watchdog timer - non-maskable interrupt and reset - free running - overflow period: 4 types selectable (125ms, 500ms, 2s, 8s)
fedl610473-07 ml610471/472/473/q471/q472/q473 2/41 ? timers - 8 bits x 2 channels [also available is 16-bit configuration (using timers 2 and 3) x 1 channels] - clock frequency measurement function mode (16-bit configuration using timers 2 and 3 x 1 channel only) ? capture - time base capture x 2 channels (4096 hz to 32 hz) ? uart - txd/rxd 1 channel - bit length, parity/no parity, odd parity/even parity, 1 stop bit/2 stop bits - positive logic/negative logic selectable - built-in baud rate generator ? rc oscillation type a/d converter - 16-bit counter - time division x 1 channels ? general-purpose ports - input-only port: 4 channels (including secondary functions) - output-only port chip or 64-pin plastic tqfp ml610471/ML610Q471: 10 channels (including secondary functions) ml610472/ml610q472: 6 channels (including secondary functions) ml610473/ml610q473: 2 channels (including secondary functions) 48-pin plastic tqfp ml610471/ML610Q471: 9 channels (including secondary functions) ml610472/ml610q472: 5 channels (including secondary functions) ml610473/ml610q473: 1 channels (including secondary functions) - input/output port chip or 64-pin plastic tqfp: 7 channels (including secondary functions) 48-pin plastic tqfp: 6 channels (including secondary functions) ? lcd driver - number of segments ml610471/ML610Q471: up to 55 dots (select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14 segments x 2 commons) ml610472/ml610q472: up to 75 dots (select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18 segments x 2 commons) ml610473/ml610q473: up to 95 dots (select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22 segments x 2 commons) - 1/1 to 1/5 duty - 1/2 or 1/3 bias (built-in bias generation circuit) - frame frequency selectable (approx. 64 hz, 73 hz, 85 hz, and 102 hz) - bias voltage multiplying clock selectable (8 types) - lcd drive stop mode, lcd display mode, all lcds on mode, and all lcds off mode selectable ? reset - reset through the reset_n pin - power-on reset generation when powered on - reset by the watchdog timer (wdt) overflow ? clock - low-speed clock (operation of this lsi is not guaranteed under a condition with no supply of low-speed crystal oscillation clock) crystal oscillation (32.768 khz) - high-speed clock built-in rc oscillation (500 khz)
fedl610473-07 ml610471/472/473/q471/q472/q473 3/41 ? power management - halt mode: suspends the instruction execution by cpu (peripheral circuits are in operating states) - stop mode: stops the low-speed oscillation and high-speed oscillation (operations of cpu and peripheral circuits are stopped.) - high-speed clock gear: the frequency of high-speed system clock can be changed by software (1/1, 1/2, 1/4, or 1/8 of the oscillation clock) - block control function: completely stops the operation of any function block circuit that is not used (resets registers and stops clock) ? shipment ? chip (die) ml610471-xxxwa / ML610Q471-xxxwa ml610472-xxxwa / ml610q472-xxxwa ml610473-xxxwa / ml610q473-xxxwa ml610471p-xxxwa / ML610Q471p-xxxwa ml610472p-xxxwa / ml610q472p-xxxwa ml610473p-xxxwa / ml610q473p-xxxwa ? 48-pin plastic tqfp ml610471-xxxtpz03a / ML610Q471-xxxtpz0aal ml610472-xxxtpz03a / ml610q472-xxxtpz0aal ml610473-xxxtpz03a / ml610q473-xxxtpz0aal ml610471p-xxxtpz03a / ML610Q471p-xxxtpz0aal ml610472p-xxxtpz03a / ml610q472p-xxxtpz0aal ml610473p-xxxtpz03a / ml610q473p-xxxtpz0aal ? 64-pin plastic tqfp ml610471-xxxtbz03a / ML610Q471-xxxtbz0arl ml610472-xxxtbz03a / ml610q472-xxxtbz0arl ml610473-xxxtbz03a / ml610q473-xxxtbz0arl ml610471p-xxxtbz03a / ML610Q471p-xxxtbz0arl ml610472p-xxxtbz03a / ml610q472p-xxxtbz0arl ml610473p-xxxtbz03a / ml610q473p-xxxtbz0arl xxx: rom code number (xxx of the blank product is nnn, mtp version only) q: mtp version p: wide range temperature version (p version) wa: chip (die) tpz0aal: 48pin plastic tqfp tbz0arl: 64pin plastic tqfp ? guaranteed operation range ? operating temperature: -20c to +70c (p version: -40c to +85c) ? operating voltage: v dd = 1.25v to 3.6v
fedl610473-07 ml610471/472/473/q471/q472/q473 4/41 block diagram ml610471/ml610472/ml610473 * secondary function or tertiary function (*1) select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14 segments x 2 commons with the register (*2) select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18 segments x 2 commons with the register (*3) select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22 segments x 2 commons with the register figure 1 ml610471/ml610472/ml610473 block diagram program memory (mask) 8kbyte ram 512 byte interrupt controller cpu (nx-u8/100) timing controller ea sp instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 2 8bit timer 2 capture 2 gpio int 5 data-bus test0 reset_n osc xt0 xt1 lsclk* power v ddl lcd driver lcd bias v l1 , v l2 , v l3 c1 , c2 rc-adc 1 rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v dd v ss int 1 display register 110bit com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg13 (ml610471) (*1) seg0 to seg17 (ml610472) (*2) seg0 to seg21 ( ml610473 ) ( *3 ) p00 to p03 p20 , p21 p35 p42 to p47 p60 to p67 (ml610471) p60 to p63 (ml610472) uart int 1 rxd0* txd0*
fedl610473-07 ml610471/472/473/q471/q472/q473 5/41 ML610Q471/ml610q472/ml610q473 * secondary function or tertiary function (*1) select among 11 segments x 5 commons, 12 segments x 4 commons, 13 segments x 3 commons, and 14 segments x 2 commons with the register (*2) select among 15 segments x 5 commons, 16 segments x 4 commons, 17 segments x 3 commons, and 18 segments x 2 commons with the register (*3) select among 19 segments x 5 commons, 20 segments x 4 commons, 21 segments x 3 commons, and 22 segments x 2 commons with the register figure 2 ML610Q471/ml610q47 2/ml610q473 block diagram program memory (flash) 8kbyte ram 512 byte interrupt controller cpu (nx-u8/100) timing controller ea sp flash writer instruction decoder bus controller instruction register tbc int 4 int 1 wdt int 2 8bit timer 2 capture 2 gpio int 5 data-bus test0 reset_n osc xt0 xt1 lsclk* power v ddl lcd driver lcd bias v l1 , v l2 , v l3 c1 , c2 rc-adc 1 rcm* cs1* in1* rs1* rt1* reset & test alu epsw1 ? 3 psw elr1 ? 3 lr ecsr1 ? 3 dsr/csr pc greg 0 ? 15 v pp v dd v ss int 1 display register 110bit com0 to com4 ( *1 )( *2 )( *3 ) seg0 to seg13 (ML610Q471) (*1) seg0 to seg17 (ml610q472) (*2) seg0 to seg21 ( ml610q473 ) ( *3 ) p00 to p03 p20 , p21 p35 p42 to p47 p60 to p67 (ML610Q471) p60 to p63 (ml610q472) uart int 1 rxd0* txd0*
fedl610473-07 ml610471/472/473/q471/q472/q473 6/41 package pin/chip pad layout ml610471/ML610Q471 48pin tqfp package pin layout (nc): no connection (*1) : ml610471 (*2) : ML610Q471 figure 3 ml610471/ML610Q471 48pin tqfp package pin layout p65 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 p66 p67 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 p64 p63 p62 p61 p60 p20 p43 p00 p01 p02 p03 nc(*1) / vpp(*2) mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 7/41 ml610471/ML610Q471 64pin tqfp package pin layout (nc): no connection (*1) : ml610471 (*2) : ML610Q471 figure 4 ml610471/ML610Q471 64pin tqfp package pin layout 12 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 nc(*1) / vpp(*2) p03 59 p02 58 p01 57 p00 56 p43 55 p42 54 p21 53 p20 52 p60 51 p61 50 p62 49 p63 p64 nc 64 63 62 61 60 nc seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 nc nc nc nc nc p65 p66 p67 nc seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 nc 29 28 27 32 31 30 18 17 21 20 19 22 33 34 35 36 37 38 39 40 41 vdd vss vddl nc xt0 nc xt1 reset_n test0 p44 p45 nc p46 p47 p35 nc nc mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 8/41 ml610472/ml610q472 48pin tqfp pin layout (nc): no connection (*1) : ml610472 (*2) : ml610q472 figure 5 ml610472/ml610q472 48pin tqfp package pin layout seg16 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg17 p63 p62 p61 p60 p20 p43 p00 p01 p02 p03 nc(*1) / vpp(*2) mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 9/41 ml610472/ml610q472 64pin tqfp pin layout (nc): no connection (*1) : ml610472 (*2) : ml610q472 figure 6 ml610472/ml610q472 64pin tqfp package pin layout 12 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 nc(*1) / vpp(*2) p03 59 p02 58 p01 57 p00 56 p43 55 p42 54 p21 53 p20 52 p60 51 p61 50 p62 49 p63 seg17 nc 64 63 62 61 60 nc seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 nc nc nc nc nc seg16 seg15 seg14 nc seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 nc 29 28 27 32 31 30 18 17 21 20 19 22 33 34 35 36 37 38 39 40 41 vdd vss vddl nc xt0 nc xt1 reset_n test0 p44 p45 nc p46 p47 p35 nc nc mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 10/41 ml610473/ml610q473 48pin tqfp pin layout (nc): no connection (*1) : ml610473 (*2) : ml610q473 figure 7 ml610473/ml610q473 48pin tqfp package pin layout seg16 12 1 2 3 4 5 6 7 8 9 10 11 25 26 27 28 29 30 31 32 33 34 35 36 24 23 22 21 20 19 18 17 16 15 14 13 38 39 40 41 42 43 44 45 46 47 48 37 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg17 seg18 seg19 seg20 seg21 p20 p43 p00 p01 p02 p03 nc(*1) / vpp(*2) mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 11/41 ml610473/ml610q473 64pin tqfp pin layout (nc): no connection (*1) : ml610473 (*2) : ml610q473 figure 8 ml610473/ml610q473 64pin tqfp package pin layout 12 1 2 3 4 5 6 7 8 9 11 42 43 44 45 46 47 48 26 25 24 23 10 14 13 16 15 nc(*1) / vpp(*2) p03 59 p02 58 p01 57 p00 56 p43 55 p42 54 p21 53 p20 52 seg21 51 seg20 50 seg19 49 seg18 seg17 nc 64 63 62 61 60 nc seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 nc nc nc nc nc seg16 seg15 seg14 nc seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 nc 29 28 27 32 31 30 18 17 21 20 19 22 33 34 35 36 37 38 39 40 41 vdd vss vddl nc xt0 nc xt1 reset_n test0 p44 p45 nc p46 p47 p35 nc nc mirror finish
fedl610473-07 ml610471/472/473/q471/q472/q473 12/41 ml610471 chip pad layout & dimension chip size: 1.61 mm 1.77 mm pad count: 49 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 9 ml610471 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 p60 45 p61 44 p62 43 p63 42 p64 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 1 2 3 4 5 6 7 8 9 12 11 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.77mm 1.61mm 35 34 p67 p02 p03 37 p65 p66 10
fedl610473-07 ml610471/472/473/q471/q472/q473 13/41 ml610472 chip pad layout & dimension chip size: 1.61 mm 1.77 mm pad count: 49 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 10 ml610472 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 p60 45 p61 44 p62 43 p63 42 seg17 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 1 2 3 4 5 6 7 8 9 12 11 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.77mm 1.61mm 35 34 seg14 p02 p03 37 seg16 seg15 10
fedl610473-07 ml610471/472/473/q471/q472/q473 14/41 ml610473 chip pad layout & dimension chip size: 1.61 mm 1.77 mm pad count: 49 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 11 ml610473 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 seg21 45 seg20 44 seg19 43 seg18 42 seg17 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 1 2 3 4 5 6 7 8 9 12 11 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.77mm 1.61mm 35 34 seg14 p02 p03 37 seg16 seg15 10
fedl610473-07 ml610471/472/473/q471/q472/q473 15/41 ML610Q471 chip pad layout & dimension (nc): no connection chip size: 1.95 mm 1.88 mm pad count: 50 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 12 ML610Q471 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 p60 45 p61 44 p62 43 p63 42 p64 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 9 1 2 3 4 5 6 7 8 10 11 12 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.88mm 1.95mm 35 34 p67 p02 p03 37 p65 p66 vpp 50 - nc - nc - nc - nc - nc - nc - nc - nc
fedl610473-07 ml610471/472/473/q471/q472/q473 16/41 ml610q472 chip pad layout & dimension (nc): no connection chip size: 1.95 mm 1.88 mm pad count: 50 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 13 ml610q472 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 p60 45 p61 44 p62 43 p63 42 seg17 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 9 1 2 3 4 5 6 7 8 10 11 12 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.88mm 1.95mm 35 34 seg14 p02 p03 37 seg16 seg15 vpp 50 - nc - nc - nc - nc - nc - nc - nc - nc
fedl610473-07 ml610471/472/473/q471/q472/q473 17/41 ml610q473 chip pad layout & dimension (nc): no connection chip size: 1.95 mm 1.88 mm pad count: 50 pins minimum pad pitch: 80 m pad aperture: 70 m70 m chip thickness: 350 m voltage of the rear side of chip: v ss level. figure 14 ml610q473 chip pin layout & dimension 18 p01 p00 p43 p42 p21 p20 46 seg21 45 seg20 44 seg19 43 seg18 42 seg17 41 40 39 38 seg4 seg3 com4/seg2 com3/seg1 com2/seg0 com1 com0 vl3 vl2 vl1 c2 c1 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 21 20 19 24 23 22 14 13 15 31 32 33 29 30 9 1 2 3 4 5 6 7 8 10 11 12 vdd vss vddl xt0 xt1 reset_n test0 p44 p45 p46 p47 p35 17 16 26 36 27 28 25 48 47 49 y x 1.88mm 1.95mm 35 34 seg14 p02 p03 37 seg16 seg15 vpp 50 - nc - nc - nc - nc - nc - nc - nc - nc
fedl610473-07 ml610471/472/473/q471/q472/q473 18/41 pad coordinates ml610471/ml610472/ml610473 pad coordinates table 1 ml610471/ml610472/ml610473 pad coordinates chip center: x=0,y=0 ml610471/2/3 ml610471/2/3 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 vdd -410 -779 30 seg10 80 779 2 vss -330 -779 31 seg11 0 779 3 vddl -250 -779 32 seg12 -80 779 4 xt0 -160 -779 33 seg13 -160 779 5 xt1 0 -779 p67 (*1) 6 reset_n -80 -779 34 seg14 (*2) (*3) -310 779 7 test0 160 -779 p66 (*1) 8 p44 260 -779 35 seg15 (*2) (*3) -390 779 9 p45 340 -779 p65 (*1) 10 p46 420 -779 36 seg16 (*2) (*3) -470 779 11 p47 500 -779 p64 (*1) 12 p35 580 -779 37 seg17 (*2) (*3) -699 587 13 c1 699 -468 p63 (*1) (*2) 14 c2 699 -388 38 seg18 (*3) -699 507 15 vl1 699 -308 p62 (*1) (*2) 16 vl2 699 -228 39 seg19 (*3) -699 427 17 vl3 699 -148 p61 (*1) (*2) 18 com0 699 133 40 seg20 (*3) -699 347 19 com1 699 213 p60 (*1) (*2) 20 com2/seg0 699 293 41 seg21 (*3) -699 267 21 com3/seg1 699 373 42 p20 -699 167 22 com4/seg2 699 453 43 p21 -699 87 23 seg3 699 533 44 p42 -699 -13 24 seg4 699 613 45 p43 -699 -93 25 seg5 480 779 46 p00 -699 -173 26 seg6 400 779 47 p01 -699 -253 27 seg7 320 779 48 p02 -699 -333 28 seg8 240 779 49 p03 -699 -413 29 seg9 160 779 (*1) pad for ml610471 . (*2) pad for ml610472. (*3) pad for ml610473.
fedl610473-07 ml610471/472/473/q471/q472/q473 19/41 ML610Q471/ml610q472/ml610q473 pad coordinates table 2 ML610Q471/ml610q472/ml610q473 pad coordinates chip center: x=0,y=0 ML610Q471/2/3 ML610Q471/2/3 pad no. pad name x ( m) y ( m) pad no. pad name x ( m) y ( m) 1 vdd -580 -834 30 seg10 250 834 2 vss -500 -834 31 seg11 170 834 3 vddl -420 -834 32 seg12 90 834 4 xt0 -330 -834 33 seg13 10 834 5 xt1 -170 -834 p67 (*1) 6 reset_n -90 -834 34 seg14 (*2) (*3) -480 834 7 test0 -10 -834 p66 (*1) 8 p44 430 -834 35 seg15 (*2) (*3) -560 834 9 p45 510 -834 p65 (*1) 10 p46 590 -834 36 seg16 (*2) (*3) -640 834 11 p47 670 -834 p64 (*1) 12 p35 750 -834 37 seg17 (*2) (*3) -869 642 13 c1 869 -523 p63 (*1) (*2) 14 c2 869 -443 38 seg18 (*3) -869 562 15 vl1 869 -363 p62 (*1) (*2) 16 vl2 869 -283 39 seg19 (*3) -869 482 17 vl3 869 -203 p61 (*1) (*2) 18 com0 869 175 40 seg20 (*3) -869 402 19 com1 869 255 p60 (*1) (*2) 20 com2/seg0 869 335 41 seg21 (*3) -869 322 21 com3/seg1 869 415 42 p20 -869 222 22 com4/seg2 869 495 43 p21 -869 142 23 seg3 869 575 44 p42 -869 42 24 seg4 869 655 45 p43 -869 -38 25 seg5 650 834 46 p00 -869 -118 26 seg6 570 834 47 p01 -869 -198 27 seg7 490 834 48 p02 -869 -278 28 seg8 410 834 49 p03 -869 -358 29 seg9 330 834 50 vpp -869 -438 (*1) pad for ML610Q471 . (*2) pad for ml610q472. (*3) pad for ml610q473.
fedl610473-07 ml610471/472/473/q471/q472/q473 20/41 pin list pin no. primary function secondary function 48 (*1) 64 (*2) pad no. (mask) pad no. (flash) pin name i/o function pin name i/o function 2 3 2 2 vss ? negative power supply pin ? ? ? 1 2 1 1 vdd ? positive power supply pin ? ? ? 3 4 3 3 vddl ? power supply pin for internal logic (internally generated) ? ? ? 48 63 ? 50 vpp (*3) ? power supply pin for flash rom ? ? ? 15 22 15 15 vl1 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? 16 23 16 16 vl2 ? power supply pin for lcd bias (internally generated or connected to positive power supply pin) (*2) ? ? ? 17 24 17 17 vl3 ? power supply pin for lcd bias (internally generated) ? ? ? 13 20 13 13 c1 ? capacitor connection pin for lcd bias generation ? ? ? 14 21 14 14 c2 ? capacitor connection pin for lcd bias generation ? ? ? 7 10 7 7 test0 i/o test pin ? ? ? 6 9 6 6 reset_n i reset input pin ? ? ? 4 6 4 4 xt0 i low-speed clock oscillation pin ? ? ? 5 8 5 5 xt1 o low-speed clock oscillation pin ? ? ? 44 59 46 46 p00/exi0/ cap0 i input port, external interrupt, capture 0 input ? ? ? 45 60 47 47 p01/exi1/ cap1 i input port, external interrupt, capture 1 input ? ? ? 46 61 48 48 p02/exi2/ rxd0 i input port, external interrupt, uart0 received data ? ? ? 47 62 49 49 p03/exi3 i input port, external interrupt ? ? ? 42 55 42 42 p20/led0 o output port lsclk o low-speed clock output ? 56 43 43 p21/led1 o output port outclk o high-speed clock output 12 15 12 12 p35 i/o input/output port rcm o rc type adc oscillation monitor ? 57 44 44 p42 i/o input/output port rxd0 ? uart0 received data 43 58 45 45 p43 i/o input/output port txd0 o uart data output 8 11 8 8 p44/ t2ck i/o input/output port, timer 2 external clock input in1 i rc type adc1 oscillation input pin 9 12 9 9 p45/t3ck i/o input/output port, timer 3 external clock input cs1 o rc type adc1 reference capacitor connection pin 10 13 10 10 p46 i/o input/output port rs1 o rc type adc1 reference resistor connection pin 11 14 11 11 p47 i/o input/output port rt1 o rc type adc1 measurement resistor sensor connection pin (*1) 48pin tqfp. (*2) 64pin tqfp (*3) pad for ML610Q471/ml610q472/ml610q473
fedl610473-07 ml610471/472/473/q471/q472/q473 21/41 pin no. primary function secondary function 48 (*1) 64 (*2) pad no. (mask) pad no. (flash) pin name i/o function pin name i/o function 18 25 18 18 com0 o lcd common pin ? ? ? 19 26 19 19 com1 o lcd common pin ? ? ? 20 27 20 20 com2/ seg0 o lcd common/segment pin ? ? ? 21 28 21 21 com3/ seg1 o lcd common/segment pin ? ? ? 22 29 22 22 com4/ seg2 o lcd common/segment pin ? ? ? 23 30 23 23 seg3 o lcd segment pin ? ? ? 24 31 24 24 seg4 o lcd segment pin ? ? ? 25 34 25 25 seg5 o lcd segment pin ? ? ? 26 35 26 26 seg6 o lcd segment pin ? ? ? 27 36 27 27 seg7 o lcd segment pin ? ? ? 28 37 28 28 seg8 o lcd segment pin ? ? ? 29 38 29 29 seg9 o lcd segment pin ? ? ? 30 39 30 30 seg10 o lcd segment pin ? ? ? 31 40 31 31 seg11 o lcd segment pin ? ? ? 32 41 32 32 seg12 o lcd segment pin ? ? ? 33 42 33 33 seg13 o lcd segment pin ? ? ? p67 (*4) output port ? ? ? 34 44 34 34 seg14 (*5)(* 6) o lcd segment pin ? ? ? p66 (*4) output port ? ? ? 35 45 35 35 seg15 (*5) (*6) o lcd segment pin ? ? ? p65 (*4) output port ? ? ? 36 46 36 36 seg16 (*5) (*6) o lcd segment pin ? ? ? p64 (*5) output port ? ? ? 37 50 37 37 seg17 (*5) (*6) o lcd segment pin ? ? ? p63 (*4) (*5) output port ? ? ? 38 51 38 38 seg18 (*6) o lcd segment pin ? ? ? p62 (*4) (*5) output port ? ? ? 39 52 39 39 seg19 (*6) o lcd segment pin ? ? ? p61 (*4) (*5) output port ? ? ? 40 53 40 40 seg20 (*6) o lcd segment pin ? ? ? p60 (*4) (*5) output port ? ? ? 41 54 41 41 seg21 (*6) o lcd segment pin ? ? ? (*1) 48pin tqfp. (*2) 64pin tqfp , (*3) pad for ML610Q471/ml610q472/ml610q473 (*4) pad for ml610471/ML610Q471 (*5) pad for ml610472/ml610q472 (*6) pad for ml610473/ml610q473.
fedl610473-07 ml610471/472/473/q471/q472/q473 22/41 pin description pin name i/o description primary/ secondary logic system reset_n i reset input pin. when this pin is set to a ?l? level, system reset mode is set and the internal section is initialized. when this pin is set to a ?h? level subsequently, program execution starts. a pull-up resistor is internally connected. ? negative xt0 i ? ? xt1 o crystal connection pin for low-speed clock. a 32.768 khz crystal resonator is connected to this pin. capacitors c dl and c gl are connected across this pin and vss. (see appendix c measuring circuit 1) ? ? lsclk o low-speed clock output. assigned to the secondary function of the p20 pin. secondary ? outclk o high-speed clock output pin. this pin is used as the secondary function of the p21 pin. secondary ? general-purpose input port p00 to p03 i general-purpose input port. primary positive general-purpose output port p20, p21 o general-purpose output port. this cannot be used as the general output port when used as the secondary function. primary positive general-purpose input/output port p35 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p42 to p47 i/o general-purpose input/output port. this cannot be used as the general input/output port when used as the secondary function. primary positive p60 to p63 o general-purpose output port. incorporated only into ml610471/610q471/ml610472/ml610q472, and not into ml610473/ml610q473. primary positive p64 to p67 o general-purpose output port. incorporated only into ml610473/ml610q473, and not into ml610471/ML610Q471/ml610472/ ml610q472. primary positive uart txd0 o uart data output pin. this pin is used as the secondary function of the p43 pin. secondary positive rxd0 i uart data input pin. this pin is used as the secondary function of the p42 or the primary function of the p02 pin. primary positive external interrupt exi0-3 i external maskable interrupt input pins. interrupt enable and edge selection can be performed for each bit by software. these pins are used as the primary functions of the p00 to p03 pins. primary/ secondary positive/ negative
fedl610473-07 ml610471/472/473/q471/q472/q473 23/41 pin name i/o description primary/ secondary logic capture cap0 i primary positive/ negative cap1 i capture trigger input pins. the value of the time base counter is captured in the register synchronously with the interrupt edge selected by software. these pins are used as the primary functions of the p00 pin(cap0) and p01 pin(cap1). primary positive/ negative timer t2ck i external clock input pin used for timer 2. this pin is used as the primary function of the p44 pin. primary ? t3ck i external clock input pin used for timer 3. this pin is used as the primary function of the p45 pin. primary ? led drive led0-1 o n-channel open drain output pins to drive led. this pin is used as the primary function of the p20 pin and p21 pin. primary positive /negative rc oscillation type a/d converter rcm o rc oscillation monitor pin. this pin is used as the secondary function of the p35 pin. secondary ? in1 i oscillation input pin of channel 1. this pin is used as the secondary function of the p44 pin. secondary ? cs1 o reference capacitor connection pin of channel 1. this pin is used as the secondary function of the p45 pin. secondary ? rs1 o reference resistor connection pin of channel 1. this pin is used as the secondary function of the p46 pin. secondary ? rt1 o resistor sensor connection pin for measurement of channel 1. this pin is used as the secondary function of the p47 pin. secondary ?
fedl610473-07 ml610471/472/473/q471/q472/q473 24/41 pin name i/o description primary/ secondary logic lcd drive signal com0 to com4 o common output pins. com2, com3, and com4 can be switched to seg0, seg1, and seg2, respectively, through the register setting. to change the setting, switch between com4 and seg2 for one pin and switch between com3, com4 and seg1, seg2 for two pins. ? ? seg0 to seg13 o segment output pin. the seg0, seg1, and seg2 pins are for switching the register setting with the com2, com3, and com4. ? ? seg14 to seg17 o segment output pin. incorporated into ml610472/ml610q472/ml610473/ml610q473, not into ml610471/ML610Q471. ? ? seg18 to seg21 o segment output pin. incorporated into ml610473/ml610q473, not into ml610471/ML610Q471/ml610472/ml610q472. ? ? lcd driver power supply vl1 ? ? ? vl2 ? ? ? vl3 ? power supply pin for lcd bias (internally generated) or power supply connection pin. depending on lcd bias setting and v dd voltage level, v dd or v ddl or capacitor is connected. for details of the connection method, see measuring circuit 1. ? ? c1 ? ? ? c2 ? power supply pins for lcd bias (internally generated). capacitor c 12 (see measuring circuit 1) is connected between c1 and c2. ? ? test test0 i/o pin for testing. a pull-down resistor is internally connected. ? positive power supply vss ? negative power supply pin. ? ? vdd ? positive power supply pin. ? ? vddl ? positive power supply pin (internally generated) for internal logic. capacitors c l0 and c l1 (see measuring circuit 1) are connected between this pin and vss. ? ? vpp ? power supply pin for programming flash rom. a pull-down resistor is internally connected. this pin is only for ML610Q471/ml610q472/ml610q473. ? ?
fedl610473-07 ml610471/472/473/q471/q472/q473 25/41 termination of unused pins table 2 shows methods of terminating the unused pins. table 2 termination of unused pins pin recommended pin handling vpp open vl1 open vl2 open vl3 open c1, c2 open reset_n open test0 pull down(1k ? to vss) p00 to p03 vdd or vss p20, p21 open p35 open p42 to p47 open p60 to p67 open com0 to com4 open seg0 to seg21 open note: it is recommended to set the unused input ports and input/output ports to the inputs with pull-down resistors/pull-up resistors or the output mode since the supply current may become excessively large if the pins are left open in the high impedance input setting.
fedl610473-07 ml610471/472/473/q471/q472/q473 26/41 electrical characteristics absolute maximum ratings (v ss = 0v) parameter symbol condition rating unit power supply voltage 1 v dd ta=25c -0.3 to +4.6 v power supply voltage 2 v pp ta=25c -0.3 to +9.5 v power supply voltage 3 v ddl ta=25c -0.3 to +3.6 v power supply voltage 4 v l1 ta=25c -0.3 to +2.0 v power supply voltage 5 v l2 ta=25c -0.3 to +4.0 v power supply voltage 6 v l3 ta=25c -0.3 to +6.0 v input voltage v in ta=25c -0.3 to v dd +0.3 v output voltage v out ta=25c -0.3 to v dd +0.3 v output current 1 i out1 port 3 to 6, ta=25c -12 to +11 ma output current 2 i out2 port 2, ta=25c -12 to +20 ma power dissipation pd ta=25c 0.9 w storage temperature t stg D -55 to +150 c recommended operating conditions (v ss = 0v) parameter symbol condition range unit without p version -20 to +70 operating temperature t op p version -40 to +85 c operating voltage v dd f op =30k to 625khz 1.25 to 3.6 v operating frequency (cpu) f op v dd =1.25 to 3.6v 30k to 625k hz low-speed crystal oscillation frequency f xtl D 32.768k hz c dl D 3 to 18 low-speed crystal oscillation external capacitance c gl D 3 to 18 pf v dd pin external capacitance c v D 1.030% to 2.230% * 1 f v ddl pin external capacitance c l D 0.4730% to 2.230% * 2 f v l1, 2, or 3 pin external capacitance c a,b,c D 0.130% f pin-to-pin (c1 to c2) external capacitance c 12 D 0.4730% f * 1 : please select as c v is larger than c l or same as c l . * 2 : when the load of vdd is small and the power rise time is too short, it may happen that the power-on reset is not generated. in this case please select c l with larger capacitance
fedl610473-07 ml610471/472/473/q471/q472/q473 27/41 operating conditions of flashrom (vss= 0v) parameter symbol condition range unit operating temperature t op at write/erase 0 to +40 c v dd at write/erase 2.75 to 3.6 v ddl at write/erase *1 2.5 to 2.75 operating voltage v pp at write/erase 7.7 to 8.3 v rewrite count c ep D 80 cycles data retention y dr D 10 years *1 : when writing to and erasing on the flash memory, the voltage in the specified range needs to be supplied to the v ddl pin. the v pp pin has an internal pull-down resistor. dc characteristics (1/6) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c typ. -10% 500 typ. +10% khz 500khz rc oscillation frequency f rc v dd =1.25 to 3.6v * 2 typ. -25% 500 typ. +25% khz low-speed crystal oscillation start time* 1 t xtl D D 0.6 2 s 500khz rc oscillation start time t rc D D D 3 s reset pulse width p rst D 200 D D reset noise elimination pulse width p nrst D D D 0.3 s power-on reset generated power rise time t por D D D 10 ms 1 * 1 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =12pf). * 2 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) reset reset_n reset_n pin reset vdd 0.9xv dd 0.1xv dd t por power on reset p rst vil1 vil1
fedl610473-07 ml610471/472/473/q471/q472/q473 28/41 dc characteristics (2/6) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit v ddl voltage v ddl fop=30k to 625khz 1.1 1.2 1.3 v v ddl temperature deviation * 1 v ddl v dd =3.0v ? -1 ? mv/c v ddl voltage dependency * 1 v ddl ? ? 5 20 mv/v 1 * 1 : the maximum v ddl voltage becomes the v dd voltage level when the v ddl voltage determined by the temperature and voltage deviations mathematically exceeds the v dd voltage.
fedl610473-07 ml610471/472/473/q471/q472/q473 29/41 dc characteristics for ml610471/472/473 (3/6) (vdd=3.0v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c D 0.3 0.8 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 D D 3 a ta=25c D 0.8 1.8 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 3 * 4 . high-speed 500khz oscillation: stopped. lcd/bias circuits: operating * 6 * 5 D D 4 a ta=25c D 3 6 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz oscillation: stopped, lcd/bias circuits: operating * 2 * 5 D D 9 a ta=25c D 50 70 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 80 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock : 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0 to blkcon4 registers are all ?1? except dlcd bit on blkcon4. * 5 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz) dc characteristics for ML610Q471/q472/q473 (4/6) (vdd=3.0v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ta=25c D 0.3 1.25 supply current 1 idd1 cpu: in stop state. low-speed/high-speed oscillation: stopped. * 5 D D 5.5 a ta=25c D 0.8 3.2 supply current 2 idd2 cpu: in halt state. (ltbc, wdt: operating)* 3 * 4 . high-speed 500khz oscillation: stopped. lcd/bias circuits: operating * 6 * 5 D D 8.5 a ta=25c D 4.7 7.5 supply current 3 idd3 cpu: in 32.768khz operating state.* 1 * 3 high-speed 500khz oscillation: stopped, lcd/bias circuits: operating * 2 * 5 D D 13 a ta=25c D 70 100 supply current 4-1 idd4-1 cpu: in 500khz rc operating state. lcd/bias circuits: operating.* 2 * 5 D D 120 a 1 * 1 : when the cpu operating rate is 100% (no halt state). * 2 : all segs: off waveform, no lcd panel load, 1/3 bias, 1/3 duty, frame frequency: approx. 64 hz, bias voltage multiplying clock : 1/128 lsclk (256hz) * 3 : 32.768khz crystal resonator dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) is used (c gl =c dl =6pf) * 4 : significant bits of blkcon0 to blkcon4 registers are all ?1? except dlcd bit on blkcon4. * 5 : recommended operating temperature (ta=-20 to 70c, ta=-40 to 85c for p version) * 6 : lcd stop mode, 1/3 bias, bias voltage multiplying clock: 1/128 lsclk (256hz)
fedl610473-07 ml610471/472/473/q471/q472/q473 30/41 dc characteristics (5/6) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit ioh1=-0.5ma, v dd =1.8 to 3.6v v dd -0.5 D D voh1 ioh1=-0.03ma, v dd =1.25 to 3.6v v dd -0.3 D D iol1=+0.5ma, v dd =1.8 to 3.6v D D 0.5 output voltage 1 (p20, p21 (n-channel open drain output mode is not selected)) (p35) (p42 to p47) (p60 to p63) *2 (p60 to p67) *1 vol1 iol1=+0.1ma, v dd =1.25 to 3.6v D D 0.3 output voltage 2 (p20, p21 (n-channel open drain output mode is selected)) vol2 iol2=+5ma, v dd =1.8 to 3.6v D D 0.5 voh3 ioh3=-0.05ma, vl1=1.2v v l3 -0.2 D D voml3 ioml3=+0.05ma, vl1=1.2v D D v l2 +0.2 voml3s ioml3s=-0.05ma, vl1=1.2v v l2 -0.2 D D volm3 iolm3=+0.05ma, vl1=1.2v D D v l1 +0.2 volm3s iolm3s=-0.05ma, vl1=1.2v v l1 -0.2 D D output voltage 3 (com0 to 4) (seg0 to 13) *1 (seg0 to 17) *2 (seg0 to 21) *3 vol3 iol3=+0.05ma, vl1=1.2v D D 0.2 v 2 iooh voh=v dd (in high-impedance state) D D 1 output leakage (p20, p21) (p35) (p42 to p47) (p60 to p63) *2 (p60 to p67) *1 iool vol=v ss (in high-impedance state) -1 D D p a 3 iih1 vih1=v dd D D 1 input current 1 (reset_n) iil1 vil1=v ss -600 -300 -2 iih2 vih2=v dd 2 300 600 input current 2 (test0) iil2 vil2=v ss -1 D D vih3=v dd, v dd =1.8 to 3.6v (when pulled-down) 2 30 200 iih3 vih3=v dd, v dd =1.25 to 3.6v (when pulled-down) 0.01 30 200 vil3=v ss, v dd =1.8 to 3.6v (when pulled-up) -200 -30 -2 iil3 vil3=v ss, v dd =1.25 to 3.6v (when pulled-up) -200 -30 -0.01 iih3z vih3=v dd (in high-impedance state) D D 1 input current 3 (p00 to p03) (p35) (p42 to p47) iil3z vil3=v ss (in high-impedance state) -1 D D p a 4 * 1 : characteristics for ml610471/ML610Q471. * 2 : characteristics for ml610472/ml610q472. * 3 : characteristics for ml610473/ml610q473.
fedl610473-07 ml610471/472/473/q471/q472/q473 31/41 dc characteristics (6/6) (vdd=1.25 to 3.6v, vss=0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit measur ement circuit vih1 D 0.7 v dd D v dd input voltage 1 (reset_n) (test0) (p00 to p03) (p35) (p42 to p47) vil1 v dd =1.25 to 3.6v 0 D 0.2 v dd v 5 input pin capacitance (p00 to p03) (p35) (p42 to p47) cin f=10khz v rms =50mv ta=25c D D 5 pf D
fedl610473-07 ml610471/472/473/q471/q472/q473 32/41 measuring circuits measuring circuit 1 measuring circuit 2 input pin v v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. *2: repeats for the specified output pin (*2) (*1) 32.768khz crystal resonator c gl c dl xt0 xt1 a v dd v ddl c l v l1 c a v l2 v l3 c c v ss c2 c1 c 12 c v : 1 f c l : 2.2uf c a ,c b ,c c : 0.1 f c 12 : 0.47 f 32.768khz crystal resonator : dt-26 (load capacitance 6pf) (made by kds:daishinku corp.) c gl , c dl : 6pf c v
fedl610473-07 ml610471/472/473/q471/q472/q473 33/41 measuring circuit 3 measuring circuit 4 input pin a v dd v ddl v l1 v l2 v l3 v ss output pin *1: repeats for the specified input pin (*1) input pin a v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. *2: repeats for the specified output pin (*2) (*1)
fedl610473-07 ml610471/472/473/q471/q472/q473 34/41 measuring circuit 5 input pin v dd v ddl v l1 v l2 v l3 v ss vih vil output pin *1: input logic circuit to determine the specified measuring conditions. (*1) waveform observation
fedl610473-07 ml610471/472/473/q471/q472/q473 35/41 ac characteristics (external interrupt) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit external interrupt disable period t nul interrupt: enabled (mie = 1), cpu: nop operation system clock: 32.768khz 76.8 D 106.8 p s ac characteristics (uart) (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit transmit baud rate t tbrt D D brt* 1 D s receive baud rate t rbrt D brt* 1 -3% brt* 1 brt* 1 +3% s * 1 : baud rate period (including the error of the clock frequency selected) set with the uart baud rate register (ua0brtl,h) and the uart mode register 0 (ua0mod0). t rbrt txd0* rxd0* *: indicates the secondary function of the port. t tbrt t nul p00?p03 (rising-edge interrupt) p00?p03 (falling-edge interrupt) p00?p03 (both-edge interrupt) t nul t nul
fedl610473-07 ml610471/472/473/q471/q472/q473 36/41 ac characteristics (rc oscillation a/d converter) condition for v dd =1.8 to 3.6v (v dd =1.8 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs1,rt1 cs0, ct0, cs1 740pf 1 ? ? k f osc1 resistor for oscillation=1k 457.3 525.2 575.1 khz f osc2 resistor for oscillation=10k 53.48 58.18 62.43 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=100k 5.43 5.89 6.32 khz kf1 rt1=1k 7.972 9.028 9.782 ? kf2 rt1=10k 0.981 1 1.019 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt1=100k 0.099 0.101 0.104 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt1-cs1 oscillation) kfx = f oscx (rs1-cs1 oscillation) , ( x = 1, 2, 3 ) v dd v ddl c l v ss c v rt1: 1k /10k /100k rs1: 10k cs1: 560pf cvr1: 820pf rcm frequency measurement (f oscx ) input pin vih vil *1: input logic circuit to determine the spec ifi ed m easu rin g co n d i t i o n s . in1 cs1 rs1 rt1 cs1 rs1 rt1 cvr1 (*1)
fedl610473-07 ml610471/472/473/q471/q472/q473 37/41 condition for v dd =1.25 to 3.6v (v dd =1.25 to 3.6v, v ss =0v, ta=-20 to +70c, ta=-40 to +85c for p version, unless otherwise specified) rating parameter symbol condition min. typ. max. unit oscillation resistor rs1,rt1 cs1 740pf 1 ? ? k f osc1 resistor for oscillation=6k 81.93 93.16 101.2 khz f osc2 resistor for oscillation=15k 35.32 38.75 41.48 khz oscillation frequency v dd = 1.5v f osc3 resistor for oscillation=105k 5.22 5.65 6.03 khz kf1 rt1=1k 2.139 2.381 2.632 ? kf2 rt1=10k 0.973 1 1.028 ? rs to rt oscillation frequency ratio *1 v dd = 1.5v kf3 rt1=100k 0.142 0.147 0.152 ? f osc1 resistor for oscillation=6k 85.28 94.58 103.3 khz f osc2 resistor for oscillation=15k 35.72 38.87 41.78 khz oscillation frequency v dd = 3.0v f osc3 resistor for oscillation=105k 5.189 5.622 6.012 khz kf1 rt1=1k 2.227 2.432 2.626 ? kf2 rt1=10k 0.982 1 1.018 ? rs to rt oscillation frequency ratio *1 v dd = 3.0v kf3 rt1=100k 0.141 0.145 0.149 ? * 1 : kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor o n the same conditions. f oscx (rt1-cs1 oscillation) kfx = f oscx (rs1-cs1 oscillation) , ( x = 1, 2, 3 ) note: k please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and in1 pin), including cvr1. especially, do not have long wiring between in1 and rs1. the coupling capacitance on the wires may occur incorr ect a/d conversion. also, please do not have signals which may be a source of noise around the node. k when rt1 (thermistor and etc.) requires long wiring due to the restricted placement, please have v ss (gnd) trace next to the signal. k please make wiring to components (capacitor, resistor, and so on) n ecessary for objective measurement. wiring to reserved components may affect to the a/d conversion operation by noise the components itself may have. rt1: 1k
/10k
/100k
ra1: 5k
rs1: 15k
cs1: 560pf cvr1: 820pf frequency measurement (f oscx ) input pin *1: input logic circuit to determine the specified measuring conditions.
v dd v ddl c l v ss c v rcm vih vil in1 cs1 rs1 rt1 cs1 rs1 cvr1 ra1 rt1
fedl610473-07 ml610471/472/473/q471/q472/q473 38/41 package dimensions 64pin tqfp package (unit: mm) p-tqfp64-1010-0.50-zk9 package material epoxy resin lead frame material cu alloy lead finish sn solder thickness more than 5 m package weight (g) 0.26typ. rev. no./last revised 1 / nov. 10,2011 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610473-07 ml610471/472/473/q471/q472/q473 39/41 48 pin tqfp package (unit: mm) p-tqfp48-0707-0.50-k package material epoxy resin lead frame material 42 alloy lead finish sn-2bi (bi 2%typ.) solder thickness more than 5 m package weight (g) 0.13typ. rev. no./last revised 3 / nov. 9,2011 notes for mounting the surface mount type package the surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact rohm?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
fedl610473-07 ml610471/472/473/q471/q472/q473 40/41 revesion history page document no. date previous edition current edition description fedl610473-01 apr.25,2011 ? ? formally edition 1 1,2,3 1,2,3 add mask rom version(ml610471/ml610472/ml610473) ? 4 add block diagram (mask rom version) ? 12,13,14 add chip pad layout and dimensions (mask rom version) fedl610473-02 may.10,2011 15,16 20,21 add pad no of mask rom version into pin list. fedl610473-03 sep.13,2011 3 3 the package name of tqfp48 was changed. 15-17, 19-21 15-17, 19-21 the pads number were changed. 28 29 add dc characterristics (ml610471/ml610472/ml610473) fedl610473-04 sep.28,2011 15-17 15-17 the figures were revised. fedl610473-05 mar.27,2012 26,32 26,32 the value of capacitor cl was changed to 2.2uf. fedl610473-06 jul.18,2012 25 25 the pull down register(1k to vss) was added. 26 26 the notes about c v , c l were added. 38,39 38,39 the package dimension was changed. fedl610473-07 jan. 7,2013 2 2 the difference of the number of the port between chip, 48-pin plastic tqfp and 64-pin plastic tqfp were added.
fedl610473-07 ml610471/472/473/q471/q472/q473 41/41 notes no copying or reproduction of this document, in part or in whole, is permitted without the consent of lapis semiconductor co., ltd. the content specified herein is subject to change for improvement without notice. the content specified herein is for the purpose of introducing la pis semiconductor's products (hereinafter "products"). if you wish to use any such product, please be sure to refer to the specifications, which can be obtained from lapis semiconductor upon request. examples of application circuits, circuit constants and any othe r information contained herein illustrate the standard usage an d operations of the products. the peripheral conditions must be taken into account when designing circuits for mass production. great care was taken in ensuring the accuracy of the information specified in this document. however, should you incur any damage arising from any inaccuracy or misprint of such information, lapis semiconductor shall bear no responsibility for such damage. the technical information specified herein is intended only to show the typical functions of and examples of application circui ts for the products. lapis semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by lapis semiconductor and other parties. lapis semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. the products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). the products specified in this document are not designed to be radiation tolerant. while lapis semiconductor always makes efforts to enhance the quality and reliability of its products, a product may fail or malfunction for a variety of reasons. please be sure to implement in your equipment using the products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any product, such as derating, redundancy, fire control and fail-safe designs. lapis semiconductor shall bear no responsibility whatsoever for your use of any product outside of the prescribed scope or not in accord ance with the instruction manual. the products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of h uman injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controlle r or other safety device). lapis semiconductor shall bear no responsibility in any way for use of any of the products for the above special purposes. if a product is intended to be used for any such special purpose, please contact a rohm sales representative before purchasing. if you intend to export or ship overseas any product or technology specified herein that may be controlled under the foreign exchange and the foreign trade law, you will be required to obtain a license or permit under the law. copyright 2011 ? 2013 lapis semiconductor co., ltd.

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